1. Field of the Invention
The present invention relates in general to computer aided integrated circuit design tools and in particular to a method for identifying inverters that may be removed from nets described by an IC design.
2. Description of Related Art
An integrated circuit (IC) designer typically employs various design tools to create a gate level netlist describing an IC by listing the circuit components (“cells”) to be formed in a semiconductor substrate and referencing the networks (“nets”) that are to interconnect the cell terminals. However the gate level netlist does not indicate how the cells are to be positioned within the substrate and does not indicate how the nets interconnecting cell terminals are to be formed and routed. Therefore, after creating a gate level netlist, the designer typically employs a computer-aided placement and routing (P&R) tool for processing the netlist to generate an IC layout design indicating how each cell is to be positioned within the semiconductor substrate and indicating how the nets interconnecting the cells are to be formed. Each net includes conductors formed on conductive layers above the substrate and may also include buffers and inverters formed as cells within the substrate.
After the P&R tool generates an IC layout, the designer may employ other tools to check the IC layout to determine whether it meets various constraints the designer has placed on the layout. One such constraint relates to signal path delay. In IC implementing synchronous logic, includes clocked devices such as registers and flip-flops for coordinating signal timing between blocks of circuit logic. FIG. 1 depicts a block of logic including a set of four gates 1–4 connected between the output of one register 5 and the input of another register 6. Register 5 allows the input signals of gates 1–4 to change state only on edges of a clock signal (CLOCK), and register 6 passes stage changes in the output signals of gates 1–4 to a next logic block only in response to edges of the CLOCK signal. Registers 5 and 6 thus control the timing of state changes in the logic block's input and output signals so that they occur only at regular, predictable intervals.
A “signal path” within an IC is the logical path a signal follows between any two nodes on the IC. The circuit of FIG. 1 has many signal paths including, for example, the signal path between output 7 of register 5 and input 8 of register 6, the path including gates 2 and 3 and the conductors 9–11 that connect those gates between register terminals 7 and 8. The path delay through that signal path is the time required for a state change in the signal at register output 7 to cause a state chance in the signal at register input 8. A typical timing constraint on that signal path would limit its path delay to less than the period of the CLOCK signal so that a state change occurring in the signal at register output 7 at the start of one CLOCK signal cycle would produce a state change at register input 8 before the start of the next clock signal cycle.
To determine whether signal paths within an IC layout meets their timing constraints, a timing analysis tool determines the delay through each gate and each net section forming each signal path having a timing constraint. The timing analysis tool consults a cell library storing information about each type of cell that may be incorporated into an IC to determine the switching delays through the cells forming the signal paths. A timing analysis tool computes the path delay through each net section based on “RC extraction data” for that net section. The delay through each net section is mainly a function of the series resistance and shunt capacitance of the conductors forming the net section, and a resistance/capacitance (RC) extraction tool processes an IC layout to produce a large RC extraction database indicating the resistance and capacitance of each section of each net based on the physical dimensions of the net section, the distance to nearby ground and power conductors and the dielectric constant of materials there between.
After finding the delay though each cell and each net section of a signal path, the timing analysis tool sums the delays to determine the total signal path delay and then compares the signal path delay to the timing constraint for that signal path. When the path delay through a particular signal path is larger than allowed by its timing constraint, the timing analysis tool attempts to reduce the delay through the signal path by inserting one or more buffers or inverters in various net segments forming the signal path. Even though a buffer or an inverter adds its own switching delay to a signal path, adding a buffer or inverter to a relatively long signal path can reduce the total amount path delay by reducing the amount of time a signal needs to charge conductor capacitance downstream of the buffer. Both buffers and inverters can reduce signal path delays, but an inverter inverts the logic state of the signal it forwards along a path while a buffer does not. Therefore, when inserting inverters into net sections forming portions of signal paths, the timing analysis tool inserts only an even number of inverters into each signal path so that it does not invert the state of the signal at the input of any cell.
When an IC layout produced by a P&R tool fails to meet all criteria, the P&R tool modifies the layout, and since modifying an IC layout can alter path delays, a timing analysis tool may have to re-determine the number, size and locations of buffers and inverters inserted into various nets that are affected by the modification. To avoid providing more buffers and inverters in signal paths than are needed, it is preferable for a timing analysis tool to remove as many buffers and inverters as possible from the signal paths described by a IC layout before it calculates signal path delays and determines whether paths require additional buffers or inverters to satisfy timing constraints. However while a timing analysis tool can remove all buffers from a net without considering effects on signal circuit logic because buffers do not affect the logic state of the signal passing through them, a timing analysis tool may not be able to remove all of the inverters from a net because inverters affect the logic state of the signal passing though them.
FIG. 2 illustrates an example net for linking its “root node” R at the output of a cell generating a logic signal to “leaf” nodes L1 and L2 at the inputs of gates that receive the logic signal. A set of inverters 12–15 and buffers 16 and 17 are included in various sections of the net to reduce the path delay between root node R and leaf nodes L1 and L2. When this net is included in a layout to be modified, all of buffers 16 and 17 can be removed without altering the logic states of the signals arriving at leaf nodes L1 and L2, but it is necessary retain one or more of inverters 12–15 in the net in order to preserve the logic states of the signals arriving at nodes L1 and L2.
What is needed is a method for quickly determining which inverters to remove from a net so as to minimize the number of inverters remaining in the net without affecting logic states of signals arriving at the net's leaf nodes.